A conventional method for forming a gate over a semiconductor substrate in a transistor includes doping impurities into both sides of the gate to form a source and a drain. In order to increase a data storage capacity while decreasing a size of semiconductor memory device, the size of each unit cell in the device is decreased.
In addition, as a result, a design rule of the capacitor and a cell transistor included in the unit cell have also been made smaller. However, such a smaller design rule applied to cell transistors has resulted in undesirable effects such as short channel effects, Drain Induced Barrier Lower (DIBL), and the like due to a decreased channel length of the cell transistor. Thus, operation of the cell transistor has become less reliable. Some of the issues caused by the decreased channel length may be relieved by maintaining a threshold voltage of the cell resistor at a substantially constant level, so that the cell transistor performs a normal operation. For example, as a channel length of the transistor decreases, a concentration of the impurities doped into a region in which the channel is formed may be increased to maintain the threshold voltage substantially constant.
However, when the design rule is 100 nm or less, if the concentration of the impurities doped into the channel region is increased, an electric field of a Storage Node (SN) junction is increased, thereby deteriorating the refresh characteristics of a semiconductor memory device.